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gen: Add option to generate DDRCTL on standalone cores 

Microwatt will want that as it uses init_done to select whether
to run the SDRAM init code or the user code at reset.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2020-05-12 21:54:54 +10:00
parent efad6b3ca5
commit d5a03b3d89
1 changed files with 3 additions and 2 deletions
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5
litedram/gen.py
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@ -303,6 +303,7 @@ class LiteDRAMCore(SoCCore):
sys_clk_freq = core_config["sys_clk_freq"] sys_clk_freq = core_config["sys_clk_freq"]
cpu_type = core_config["cpu"] cpu_type = core_config["cpu"]
cpu_variant = core_config.get("cpu_variant", "standard") cpu_variant = core_config.get("cpu_variant", "standard")
had_ddrctl = core_config.get("has_ddrctl", False)
if cpu_type is None: if cpu_type is None:
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0 kwargs["integrated_sram_size"] = 0
@ -368,7 +369,7 @@ class LiteDRAMCore(SoCCore):
) )
# DRAM Control/Status ---------------------------------------------------------------------- # DRAM Control/Status ----------------------------------------------------------------------
if cpu_type is not None: if cpu_type is not None or had_ddrctl:
# Expose calibration status to user. # Expose calibration status to user.
self.submodules.ddrctrl = LiteDRAMCoreControl() self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl") self.add_csr("ddrctrl")
@ -376,7 +377,7 @@ class LiteDRAMCore(SoCCore):
platform.request("init_done").eq(self.ddrctrl.init_done.storage), platform.request("init_done").eq(self.ddrctrl.init_done.storage),
platform.request("init_error").eq(self.ddrctrl.init_error.storage) platform.request("init_error").eq(self.ddrctrl.init_error.storage)
] ]
else: if cpu_type is None:
# Expose bus interface to user. # Expose bus interface to user.
wb_bus = wishbone.Interface() wb_bus = wishbone.Interface()
self.bus.add_master(master=wb_bus) self.bus.add_master(master=wb_bus)