Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen: Add option to specify CSR base for standalone cores 

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2020-05-12 21:54:11 +10:00
parent c91cbb597d
commit efad6b3ca5
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litedram/gen.py
View File

@ -309,11 +309,13 @@ class LiteDRAMCore(SoCCore):
kwargs["with_uart"] = False
kwargs["with_timer"] = False
kwargs["with_ctrl"] = False
csr_base = core_config.get("csr_base", 0)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
cpu_type = cpu_type,
cpu_variant = cpu_variant,
cpu_type = cpu_type,
cpu_variant = cpu_variant,
csr_base = csr_base,
**kwargs)
# CRG --------------------------------------------------------------------------------------