Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

modules/mt40a1g8: use _L (long) timings

This commit is contained in:
Florent Kermarrec 2019-02-12 11:26:48 +01:00
parent 2d4fdd1de4
commit d89b17177a
1 changed files with 1 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
litedram/modules.py
View File

@ -373,15 +373,6 @@ class EDY4016A(SDRAMModule):
class MT40A1G8(SDRAMModule): class MT40A1G8(SDRAMModule):
# param | prodesign | this
# tFAW | 30n | 20, 21, 25
# tRAS | 32n | 32
# tRCD | 13.32n | 13.32, 13.5
# tREFI | 7.8u | 7.825u
# tRFC | 350 | 350
# tRP | 13.32n | 13.32, 13.5
# tRRD | 3.3, 6.4 | 4, 4.9
# tWTR | 2.5, 7.5 | 4, 7.5
memtype = "DDR4" memtype = "DDR4"
# geometry # geometry
ngroupbanks = 4 ngroupbanks = 4
@ -390,7 +381,7 @@ class MT40A1G8(SDRAMModule):
nrows = 65536 nrows = 65536
ncols = 1024 ncols = 1024
# timings # timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2.5, 7.5), tCCD=(4, None), tRRD=(3.3, 6.4)) technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6.4))
speedgrade_timings = { speedgrade_timings = {
"2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=350, tFAW=(20, 25), tRAS=32), "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=350, tFAW=(20, 25), tRAS=32),
"2666": _SpeedgradeTimings(tRP=13.50, tRCD=13.50, tWR=15, tRFC=350, tFAW=(20, 21), tRAS=32), "2666": _SpeedgradeTimings(tRP=13.50, tRCD=13.50, tWR=15, tRFC=350, tFAW=(20, 21), tRAS=32),