frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade).
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@ -104,7 +104,7 @@ class LiteDRAMDMAReader(Module, AutoCSR):
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self.submodules += fifo
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self.submodules += fifo
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self.comb += [
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self.comb += [
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rdata.connect(fifo.sink, omit={"id", "resp"}),
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rdata.connect(fifo.sink, omit={"id", "resp", "dest", "user"}),
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fifo.source.connect(source, omit={"ready"}),
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fifo.source.connect(source, omit={"ready"}),
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fifo.source.ready.eq(source.ready | ~enable), # Flush FIFO/Reservation counter when disabled.
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fifo.source.ready.eq(source.ready | ~enable), # Flush FIFO/Reservation counter when disabled.
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data_dequeued.eq(fifo.source.valid & fifo.source.ready)
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data_dequeued.eq(fifo.source.valid & fifo.source.ready)
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