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frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade).

This commit is contained in:
Florent Kermarrec 2023-01-16 11:21:47 +01:00
parent b749e10970
commit d95c1fc583
1 changed files with 1 additions and 1 deletions
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litedram/frontend/dma.py
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@ -104,7 +104,7 @@ class LiteDRAMDMAReader(Module, AutoCSR):
self.submodules += fifo self.submodules += fifo
self.comb += [ self.comb += [
rdata.connect(fifo.sink, omit={"id", "resp"}), rdata.connect(fifo.sink, omit={"id", "resp", "dest", "user"}),
fifo.source.connect(source, omit={"ready"}), fifo.source.connect(source, omit={"ready"}),
fifo.source.ready.eq(source.ready | ~enable), # Flush FIFO/Reservation counter when disabled. fifo.source.ready.eq(source.ready | ~enable), # Flush FIFO/Reservation counter when disabled.
data_dequeued.eq(fifo.source.valid & fifo.source.ready) data_dequeued.eq(fifo.source.valid & fifo.source.ready)