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frontend_fifo: Fix dram_data_cnt signal size.

This commit is contained in:
Florent Kermarrec 2021-09-23 18:55:51 +02:00
parent 49cf76af84
commit d9ec9882af
1 changed files with 1 additions and 1 deletions
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2
litedram/frontend/fifo.py
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@ -299,7 +299,7 @@ class LiteDRAMFIFO(Module):
) )
dram_data_inc = Signal() dram_data_inc = Signal()
dram_data_dec = Signal() dram_data_dec = Signal()
dram_data_cnt = Signal(int(math.log2(depth))) dram_data_cnt = Signal(int(math.log2(depth + writer_fifo_depth + reader_fifo_depth) + 1))
self.sync += dram_data_cnt.eq(dram_data_cnt + dram_data_inc - dram_data_dec) self.sync += dram_data_cnt.eq(dram_data_cnt + dram_data_inc - dram_data_dec)
fsm.act("DRAM", fsm.act("DRAM",
# Increment DRAM Data Count on Pre-Converter's Sink cycle. # Increment DRAM Data Count on Pre-Converter's Sink cycle.