Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen: fix default csr_port_align value

This commit is contained in:
Florent Kermarrec 2019-09-23 09:05:54 +02:00
parent bac66aa08f
commit da408a3982
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litedram/gen.py
View File

@ -248,7 +248,7 @@ class LiteDRAMCore(SoCSDRAM):
def __init__(self, platform, core_config, **kwargs): def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios()) platform.add_extension(get_common_ios())
sys_clk_freq = core_config["sys_clk_freq"] sys_clk_freq = core_config["sys_clk_freq"]
csr_align = core_config.get("csr_port_align", "32") csr_align = core_config.get("csr_port_align", 32)
SoCSDRAM.__init__(self, platform, sys_clk_freq, SoCSDRAM.__init__(self, platform, sys_clk_freq,
cpu_type=core_config["cpu"], cpu_type=core_config["cpu"],
l2_size=16*core_config["sdram_module_nb"], l2_size=16*core_config["sdram_module_nb"],