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gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore

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Florent Kermarrec 2019-09-23 12:55:14 +02:00
parent adf481f1d5
commit db97203877
4 changed files with 14 additions and 8 deletions
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4
examples/arty.yml
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@ -34,6 +34,6 @@
"user_ports_id_width": 32, # AXI identifier width "user_ports_id_width": 32, # AXI identifier width
# CSR Port ----------------------------------------------------------------- # CSR Port -----------------------------------------------------------------
"csr_expose": "no", # Expose CSR bus as I/Os "csr_expose": "False", # Expose CSR bus as I/Os
"csr_align" : 32, # CSR alignment "csr_align" : 32, # CSR alignment
} }

4
examples/genesys2.yml
View file

@ -34,6 +34,6 @@
"user_ports_id_width": 32, # AXI identifier width "user_ports_id_width": 32, # AXI identifier width
# CSR Port ----------------------------------------------------------------- # CSR Port -----------------------------------------------------------------
"csr_expose": "no", # Expose CSR bus as I/Os "csr_expose": "False", # Expose CSR bus as I/Os
"csr_align" : 32, # CSR alignment "csr_align" : 32, # CSR alignment
} }

4
examples/nexys4ddr.yml
View file

@ -29,6 +29,6 @@
"user_ports_id_width": 32, # AXI identifier width "user_ports_id_width": 32, # AXI identifier width
# CSR Port ----------------------------------------------------------------- # CSR Port -----------------------------------------------------------------
"csr_expose": "no", # Expose CSR bus as I/Os "csr_expose": "False", # Expose CSR bus as I/Os
"csr_align" : 32, # CSR alignment "csr_align" : 32, # CSR alignment
} }

10
litedram/gen.py
View file

@ -249,14 +249,16 @@ class LiteDRAMCore(SoCSDRAM):
platform.add_extension(get_common_ios()) platform.add_extension(get_common_ios())
sys_clk_freq = core_config["sys_clk_freq"] sys_clk_freq = core_config["sys_clk_freq"]
cpu_type = core_config["cpu"] cpu_type = core_config["cpu"]
csr_expose = core_config.get("csr_expose", False)
csr_align = core_config.get("csr_align", 32) csr_align = core_config.get("csr_align", 32)
if cpu_type == "None": if cpu_type is None:
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0 kwargs["integrated_sram_size"] = 0
kwargs["l2_size"] = 0 kwargs["l2_size"] = 0
kwargs["with_uart"] = False kwargs["with_uart"] = False
kwargs["with_timer"] = False kwargs["with_timer"] = False
kwargs["with_ctrl"] = False kwargs["with_ctrl"] = False
kwargs["with_wishbone"] = (cpu_type is None)
else: else:
kwargs["l2_size"] = 0 kwargs["l2_size"] = 0
SoCSDRAM.__init__(self, platform, sys_clk_freq, SoCSDRAM.__init__(self, platform, sys_clk_freq,
@ -300,7 +302,7 @@ class LiteDRAMCore(SoCSDRAM):
] ]
# CSR port # CSR port
if core_config.get("csr_expose", "no") == "yes": if csr_expose:
csr_port = csr_bus.Interface( csr_port = csr_bus.Interface(
address_width=self.csr_address_width, address_width=self.csr_address_width,
data_width=self.csr_data_width) data_width=self.csr_data_width)
@ -438,6 +440,10 @@ def main():
# Convert YAML elements to Python/LiteX # Convert YAML elements to Python/LiteX
for k, v in core_config.items(): for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
if "clk_freq" in k: if "clk_freq" in k:
core_config[k] = float(core_config[k]) core_config[k] = float(core_config[k])
if k == "sdram_module": if k == "sdram_module":