modules: add M12L16161A

This commit is contained in:
Florent Kermarrec 2020-01-22 16:31:13 +01:00
parent ba9134a9a8
commit dc16d971ad
1 changed files with 10 additions and 1 deletions

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@ -210,6 +210,16 @@ class M12L64322A(SDRAMModule):
technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10)) technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
class M12L16161A(SDRAMModule):
memtype = "SDR"
# geometry
nbanks = 2
nrows = 2048
ncols = 256
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
# DDR ---------------------------------------------------------------------------------------------- # DDR ----------------------------------------------------------------------------------------------
class MT46V32M16(SDRAMModule): class MT46V32M16(SDRAMModule):
@ -290,7 +300,6 @@ class P3R1GE4JGF(SDRAMModule):
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None) technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=12.5, tRCD=12.5, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=12.5, tRCD=12.5, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
# DDR3 (Chips) ------------------------------------------------------------------------------------- # DDR3 (Chips) -------------------------------------------------------------------------------------
class MT41K64M16(SDRAMModule): class MT41K64M16(SDRAMModule):