modules: add M12L16161A
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@ -210,6 +210,16 @@ class M12L64322A(SDRAMModule):
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technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
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technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
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class M12L16161A(SDRAMModule):
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memtype = "SDR"
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# geometry
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nbanks = 2
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nrows = 2048
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ncols = 256
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
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# DDR ----------------------------------------------------------------------------------------------
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# DDR ----------------------------------------------------------------------------------------------
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class MT46V32M16(SDRAMModule):
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class MT46V32M16(SDRAMModule):
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@ -290,7 +300,6 @@ class P3R1GE4JGF(SDRAMModule):
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=12.5, tRCD=12.5, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=12.5, tRCD=12.5, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
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# DDR3 (Chips) -------------------------------------------------------------------------------------
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# DDR3 (Chips) -------------------------------------------------------------------------------------
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class MT41K64M16(SDRAMModule):
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class MT41K64M16(SDRAMModule):
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