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bench: Update with recent changes.

This commit is contained in:
Florent Kermarrec 2021-03-12 10:25:11 +01:00
parent e3c2ab0757
commit df5f555842
5 changed files with 7 additions and 19 deletions
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4
bench/arty.py
View File

@ -74,7 +74,6 @@ class BenchSoC(SoCCore):
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
csr_data_width = 32,
uart_name = uart)
# CRG --------------------------------------------------------------------------------------
@ -91,8 +90,7 @@ class BenchSoC(SoCCore):
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
with_bist = with_bist,
)
with_bist = with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":

4
bench/genesys2.py
View File

@ -68,7 +68,6 @@ class BenchSoC(SoCCore):
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
csr_data_width = 32,
uart_name = uart)
# CRG --------------------------------------------------------------------------------------
@ -85,8 +84,7 @@ class BenchSoC(SoCCore):
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
with_bist = with_bist,
)
with_bist = with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":

4
bench/kc705.py
View File

@ -68,7 +68,6 @@ class BenchSoC(SoCCore):
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
csr_data_width = 32,
uart_name = uart)
# CRG --------------------------------------------------------------------------------------
@ -85,8 +84,7 @@ class BenchSoC(SoCCore):
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
with_bist = with_bist,
)
with_bist = with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":

7
bench/kcu105.py
View File

@ -43,7 +43,7 @@ class _CRG(Module, AutoCSR):
self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
main_pll.register_clkin(platform.request("clk125"), 125e6)
main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
main_pll.create_clkout(self.cd_idelay, 200e6, with_reset=False)
main_pll.create_clkout(self.cd_idelay, 200e6)
main_pll.create_clkout(self.cd_uart, 100e6)
main_pll.create_clkout(self.cd_eth, 200e6)
main_pll.expose_drp()
@ -65,7 +65,6 @@ class _CRG(Module, AutoCSR):
i_I = self.cd_pll4x.clk,
o_O = self.cd_sys4x.clk,
),
AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
@ -87,7 +86,6 @@ class BenchSoC(SoCCore):
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
csr_data_width = 32,
uart_name = uart)
# CRG --------------------------------------------------------------------------------------
@ -105,8 +103,7 @@ class BenchSoC(SoCCore):
module = EDY4016A(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = 0x40000000,
with_bist = with_bist,
)
with_bist = with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":

7
bench/xcu1525.py
View File

@ -40,7 +40,7 @@ class _CRG(Module, AutoCSR):
self.submodules.main_pll = main_pll = USPMMCM(speedgrade=-2)
main_pll.register_clkin(platform.request("clk300", channel), 300e6)
main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
main_pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
main_pll.create_clkout(self.cd_idelay, 500e6)
main_pll.create_clkout(self.cd_uart, 100e6)
main_pll.expose_drp()
@ -61,7 +61,6 @@ class _CRG(Module, AutoCSR):
i_I = self.cd_pll4x.clk,
o_O = self.cd_sys4x.clk,
),
AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
@ -83,7 +82,6 @@ class BenchSoC(SoCCore):
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
csr_data_width = 32,
uart_name = uart)
# CRG --------------------------------------------------------------------------------------
@ -101,8 +99,7 @@ class BenchSoC(SoCCore):
module = MT40A512M8(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = 0x40000000,
with_bist = with_bist,
)
with_bist = with_bist)
# Workaround for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")