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litedram_gen: Fix rate for 7-Series.

This commit is contained in:
Florent Kermarrec 2021-10-07 16:22:40 +02:00
parent 1c59e77302
commit e1defa2687
1 changed files with 1 additions and 1 deletions
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2
litedram/gen.py
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@ -535,7 +535,7 @@ class LiteDRAMCore(SoCCore):
rate = {"DDR3": "1:2"}[core_config["memtype"]] rate = {"DDR3": "1:2"}[core_config["memtype"]]
elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]: elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
crg = LiteDRAMS7DDRPHYCRG(platform, core_config) crg = LiteDRAMS7DDRPHYCRG(platform, core_config)
rate = {"DDR3": "1:4", "DDR4": "1:4"}[core_config["memtype"]] rate = {"DDR2": "1:2", "DDR3": "1:4"}[core_config["memtype"]]
elif core_config["sdram_phy"] in [litedram_phys.USDDRPHY]: elif core_config["sdram_phy"] in [litedram_phys.USDDRPHY]:
crg = LiteDRAMUSDDRPHYCRG(platform, core_config) crg = LiteDRAMUSDDRPHYCRG(platform, core_config)
rate = {"DDR3": "1:4", "DDR4": "1:4"}[core_config["memtype"]] rate = {"DDR3": "1:4", "DDR4": "1:4"}[core_config["memtype"]]