test/test_axi: move definitions to top and make Access herit from Burst
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@ -3,7 +3,7 @@ import random
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from migen import *
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from litedram.common import LiteDRAMNativePort
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from litedram.common import *
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from litedram.frontend.axi import *
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from test.common import *
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@ -11,32 +11,49 @@ from test.common import *
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from litex.gen.sim import *
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class Burst:
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def __init__(self, addr, type=burst_types["fixed"], len=0, size=0):
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self.addr = addr
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self.type = type
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self.len = len
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self.size = size
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def to_beats(self):
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r = []
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for i in range(self.len + 1):
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if self.type == burst_types["incr"]:
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offset = i*2**(self.size)
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r += [Beat(self.addr + offset)]
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elif self.type == burst_types["wrap"]:
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offset = (i*2**(self.size))%((2**self.size)*(self.len))
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r += [Beat(self.addr + offset)]
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else:
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r += [Beat(self.addr)]
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return r
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class Beat:
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def __init__(self, addr):
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self.addr = addr
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class Access(Burst):
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def __init__(self, addr, data, id, **kwargs):
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Burst.__init__(self, addr, **kwargs)
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self.data = data
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self.id = id
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class Write(Access):
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pass
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class Read(Access):
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pass
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class TestAXI(unittest.TestCase):
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def test_burst2beat(self):
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class Beat:
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def __init__(self, addr):
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self.addr = addr
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class Burst:
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def __init__(self, type, addr, len, size):
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self.type = type
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self.addr = addr
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self.len = len
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self.size = size
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def to_beats(self):
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r = []
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for i in range(self.len + 1):
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if self.type == burst_types["incr"]:
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offset = i*2**(self.size)
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r += [Beat(self.addr + offset)]
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elif self.type == burst_types["wrap"]:
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offset = (i*2**(self.size))%((2**self.size)*(self.len))
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r += [Beat(self.addr + offset)]
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else:
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r += [Beat(self.addr)]
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return r
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def bursts_generator(ax, bursts, valid_rand=50):
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prng = random.Random(42)
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for burst in bursts:
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@ -78,9 +95,9 @@ class TestAXI(unittest.TestCase):
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prng = random.Random(42)
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bursts = []
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for i in range(32):
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bursts.append(Burst(burst_types["fixed"], prng.randrange(2**32), prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(burst_types["incr"], prng.randrange(2**32), prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(burst_types["wrap"], 4, 4-1, log2_int(2)))
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bursts.append(Burst(prng.randrange(2**32), burst_types["fixed"], prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(prng.randrange(2**32), burst_types["incr"], prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(4, burst_types["wrap"], 4-1, log2_int(2)))
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# generate expexted dut output (beats for reference)
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beats = []
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@ -96,18 +113,6 @@ class TestAXI(unittest.TestCase):
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self.assertEqual(self.errors, 0)
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def test_axi2native(self):
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class Access:
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def __init__(self, addr, data, id):
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self.addr = addr
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self.data = data
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self.id = id
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class Write(Access):
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pass
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class Read(Access):
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pass
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def writes_cmd_generator(axi_port, writes):
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for write in writes:
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# send command
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