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phy/usddrphy: Add missing i_RST on DQS's ODELAYE3.

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Florent Kermarrec 2021-03-04 14:44:07 +01:00
parent 06411b2a72
commit e3c2ab0757
1 changed files with 1 additions and 0 deletions
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litedram/phy/usddrphy.py
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@ -288,6 +288,7 @@ class USDDRPHY(Module, AutoCSR):
p_DELAY_TYPE = "VARIABLE", p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = int(tck*1e12/4), p_DELAY_VALUE = int(tck*1e12/4),
o_CNTVALUEOUT = self._half_sys8x_taps.status if (i == 0) and (j == 0) else Signal(), o_CNTVALUEOUT = self._half_sys8x_taps.status if (i == 0) and (j == 0) else Signal(),
i_RST = ResetSignal("ic"),
i_CLK = ClockSignal(), i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage, i_EN_VTC = self._en_vtc.storage,
i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re, i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re,