gen: fix LiteDRAMFIFO parameters

2020-06-03 17:39:45 +02:00 · 2020-06-03 17:39:45 +02:00 · e5179eb9ab
parent 8fedc3fcd2
commit e5179eb9ab
1 changed files with 0 additions and 2 deletions
--- a/litedram/gen.py
+++ b/litedram/gen.py
@ -609,9 +609,7 @@ class LiteDRAMCore(SoCCore):
                    base            = port["base"],
                    depth           = port["depth"],
                    write_port      = self.sdram.crossbar.get_port("write"),
-                    write_threshold = port["depth"] - 32, # FIXME
                    read_port       = self.sdram.crossbar.get_port("read"),
-                    read_threshold  = 32 # FIXME
                )
                self.submodules += fifo
                self.comb += [