gen: fix LiteDRAMFIFO parameters
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@ -609,9 +609,7 @@ class LiteDRAMCore(SoCCore):
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base = port["base"],
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base = port["base"],
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depth = port["depth"],
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depth = port["depth"],
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write_port = self.sdram.crossbar.get_port("write"),
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write_port = self.sdram.crossbar.get_port("write"),
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write_threshold = port["depth"] - 32, # FIXME
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read_port = self.sdram.crossbar.get_port("read"),
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read_port = self.sdram.crossbar.get_port("read"),
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read_threshold = 32 # FIXME
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)
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)
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self.submodules += fifo
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self.submodules += fifo
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self.comb += [
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self.comb += [
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