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README: update

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Florent Kermarrec 2018-09-03 14:17:03 +02:00
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@ -26,8 +26,7 @@ design flow by generating the verilog rtl that you will use as a standard core.
PHY: PHY:
- Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice) - Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice)
- Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio) - Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
- Kintex7 DDR3 PHY (1:4 frequency ratio) - Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
- Artix7 DDR3 PHY (1:4 frequency ratio)
Core: Core:
- Fully pipelined, high performance. - Fully pipelined, high performance.
- Configurable commands depth on bankmachines. - Configurable commands depth on bankmachines.