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phy/ecp5ddrphy: remove Bitslip from comment (no longer present).

This commit is contained in:
Florent Kermarrec 2020-04-16 08:51:26 +02:00
parent f4f2948f61
commit eca7fc2ddc
1 changed files with 1 additions and 1 deletions
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litedram/phy/ecp5ddrphy.py
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@ -454,7 +454,7 @@ class ECP5DDRPHY(Module, AutoCSR):
# the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2) # the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2)
# #
# The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI # The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI
# interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA and Bitslip latencies. # interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies.
rddata_en_last = Signal.like(rddata_en) rddata_en_last = Signal.like(rddata_en)
self.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last)) self.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last))
self.sync += rddata_en_last.eq(rddata_en) self.sync += rddata_en_last.eq(rddata_en)