Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/lpddr5/sim: fix double reset with check_timings=False at high frequency

This commit is contained in:
Jędrzej Boczar 2021-09-06 15:31:30 +02:00 committed by Alessandro Comodi
parent 43aef6255e
commit ed6c7759b5
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litedram/phy/lpddr5/sim.py
View File

@ -321,7 +321,8 @@ class CommandsSim(Module, AutoCSR):
self.submodules.tinit4 = PulseTiming(5) # (min) stabilized CK before CS high; not really applicable in this simulation self.submodules.tinit4 = PulseTiming(5) # (min) stabilized CK before CS high; not really applicable in this simulation
self.submodules.tinit5 = PulseTiming(ck(2*us)) # (min) idle time before first MRW/MRR cmmand self.submodules.tinit5 = PulseTiming(ck(2*us)) # (min) idle time before first MRW/MRR cmmand
self.submodules.tzqlat = PulseTiming(max(4, ck(30*ns))) # (min) ZQCAL latch quiet time self.submodules.tzqlat = PulseTiming(max(4, ck(30*ns))) # (min) ZQCAL latch quiet time
self.submodules.tpw_reset = PulseTiming(ck(100*ns)) # (min) RESET_n low time for Reset initialization with stable power tpw_reset_ck = ck(100*ns) if check_timings else 4 # Avoids double reset during initialization at high frequecies
self.submodules.tpw_reset = PulseTiming(tpw_reset_ck) # (min) RESET_n low time for Reset initialization with stable power
def with_progress(timing, string, *args, as_clocks=False): def with_progress(timing, string, *args, as_clocks=False):
current, full = timing.progress() current, full = timing.progress()