Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted)

This commit is contained in:
Florent Kermarrec 2018-08-29 14:15:12 +02:00
parent c37d3af5b5
commit ed7eef12d4
1 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
litedram/phy/s7ddrphy.py
View File

@ -433,11 +433,12 @@ class S7DDRPHY(Module, AutoCSR):
]
# dqs preamble/postamble
dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency
self.comb += [
dqs_preamble.eq(last_wrdata_en[cwl_sys_latency-1] &
~last_wrdata_en[cwl_sys_latency]),
dqs_postamble.eq(last_wrdata_en[cwl_sys_latency+1] &
~last_wrdata_en[cwl_sys_latency]),
dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] &
~last_wrdata_en[dqs_sys_latency]),
dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+1] &
~last_wrdata_en[dqs_sys_latency]),
]