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Merge pull request #193 from ozbenh/standalone-cores 

Improve standalone cores
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enjoy-digital 2020-05-12 14:56:40 +02:00 committed by GitHub
parent 4e539ad76e 04717b478b
commit f036ec2c26
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1 changed files with 12 additions and 8 deletions
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litedram/gen.py
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@ -303,18 +303,22 @@ class LiteDRAMCore(SoCCore):
sys_clk_freq = core_config["sys_clk_freq"] sys_clk_freq = core_config["sys_clk_freq"]
cpu_type = core_config["cpu"] cpu_type = core_config["cpu"]
cpu_variant = core_config.get("cpu_variant", "standard") cpu_variant = core_config.get("cpu_variant", "standard")
bus_expose = core_config.get("bus_expose", False) had_ddrctl = core_config.get("has_ddrctl", False)
csr_align = core_config.get("csr_align", 32)
if cpu_type is None: if cpu_type is None:
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0 kwargs["integrated_sram_size"] = 0
kwargs["with_uart"] = False kwargs["with_uart"] = False
kwargs["with_timer"] = False kwargs["with_timer"] = False
kwargs["with_ctrl"] = False kwargs["with_ctrl"] = False
csr_base = core_config.get("csr_base", 0)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
cpu_type = cpu_type, cpu_type = cpu_type,
cpu_variant = cpu_variant, cpu_variant = cpu_variant,
csr_base = csr_base,
csr_alignment = csr_align,
**kwargs) **kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
@ -367,7 +371,7 @@ class LiteDRAMCore(SoCCore):
) )
# DRAM Control/Status ---------------------------------------------------------------------- # DRAM Control/Status ----------------------------------------------------------------------
if cpu_type is not None: if cpu_type is not None or had_ddrctl:
# Expose calibration status to user. # Expose calibration status to user.
self.submodules.ddrctrl = LiteDRAMCoreControl() self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl") self.add_csr("ddrctrl")
@ -375,12 +379,12 @@ class LiteDRAMCore(SoCCore):
platform.request("init_done").eq(self.ddrctrl.init_done.storage), platform.request("init_done").eq(self.ddrctrl.init_done.storage),
platform.request("init_error").eq(self.ddrctrl.init_error.storage) platform.request("init_error").eq(self.ddrctrl.init_error.storage)
] ]
else: if cpu_type is None:
# Expose bus interface to user. # Expose bus interface to user.
wb_bus = wishbone.Interface() wb_bus = wishbone.Interface(adr_width = self.csr.address_width)
self.bus.add_master(master=wb_bus) self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb")) platform.add_extension(wb_bus.get_ios("wb_ctrl"))
wb_pads = platform.request("wb") wb_pads = platform.request("wb_ctrl")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave") self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# User ports ------------------------------------------------------------------------------- # User ports -------------------------------------------------------------------------------