core/bandwidth: avoid missing a command
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@ -14,8 +14,8 @@ from litex.soc.interconnect.csr import *
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class Bandwidth(Module, AutoCSR):
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def __init__(self, cmd, data_width, period_bits=24):
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self.update = CSR()
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self.nreads = CSRStatus(period_bits)
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self.nwrites = CSRStatus(period_bits)
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self.nreads = CSRStatus(period_bits + 1)
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self.nwrites = CSRStatus(period_bits + 1)
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self.data_width = CSRStatus(bits_for(data_width), reset=data_width)
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# # #
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@ -33,17 +33,22 @@ class Bandwidth(Module, AutoCSR):
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counter = Signal(period_bits)
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period = Signal()
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nreads = Signal(period_bits)
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nwrites = Signal(period_bits)
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nreads_r = Signal(period_bits)
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nwrites_r = Signal(period_bits)
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nreads = Signal(period_bits + 1)
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nwrites = Signal(period_bits + 1)
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nreads_r = Signal(period_bits + 1)
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nwrites_r = Signal(period_bits + 1)
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self.sync += [
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Cat(counter, period).eq(counter + 1),
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If(period,
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nreads_r.eq(nreads),
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nwrites_r.eq(nwrites),
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nreads.eq(0),
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nwrites.eq(0)
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nwrites.eq(0),
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# don't miss command if there is one on period boundary
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If(cmd_valid & cmd_ready,
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If(cmd_is_read, nreads.eq(1)),
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If(cmd_is_write, nwrites.eq(1)),
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)
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).Elif(cmd_valid & cmd_ready,
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If(cmd_is_read, nreads.eq(nreads + 1)),
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If(cmd_is_write, nwrites.eq(nwrites + 1)),
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