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dma: expose reservation level in the reader

This commit is contained in:
Ilia Sergachev 2019-07-05 09:57:13 +02:00
parent f018c9e268
commit f145287fdc
1 changed files with 7 additions and 4 deletions
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11
litedram/frontend/dma.py
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@ -39,6 +39,9 @@ class LiteDRAMDMAReader(Module):
source : Record("data") source : Record("data")
Source for DRAM word results from reading. Source for DRAM word results from reading.
rsv_level: Signal()
FIFO reservation level counter
""" """
def __init__(self, port, fifo_depth=16, fifo_buffered=False): def __init__(self, port, fifo_depth=16, fifo_buffered=False):
@ -74,15 +77,15 @@ class LiteDRAMDMAReader(Module):
# incremented when data is planned to be queued # incremented when data is planned to be queued
# decremented when data is dequeued # decremented when data is dequeued
data_dequeued = Signal() data_dequeued = Signal()
rsv_level = Signal(max=fifo_depth+1) self.rsv_level = Signal(max=fifo_depth+1)
self.sync += [ self.sync += [
If(request_issued, If(request_issued,
If(~data_dequeued, rsv_level.eq(rsv_level + 1)) If(~data_dequeued, self.rsv_level.eq(self.rsv_level + 1))
).Elif(data_dequeued, ).Elif(data_dequeued,
rsv_level.eq(rsv_level - 1) self.rsv_level.eq(self.rsv_level - 1)
) )
] ]
self.comb += request_enable.eq(rsv_level != fifo_depth) self.comb += request_enable.eq(self.rsv_level != fifo_depth)
# FIFO # FIFO
fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered) fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered)