lpddr4: remove old fixme comments
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a64cb58753
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@ -122,7 +122,7 @@ class LPDDR4PHY(Module, AutoCSR):
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bitslip_cycles = 1
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bitslip_cycles = 1
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bitslip_range = 1
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bitslip_range = 1
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# Commands are sent over 4 DRAM clocks (sys8x) and we count cl/cwl from last bit
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# Commands are sent over 4 DRAM clocks (sys8x) and we count cl/cwl from last bit
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cmd_latency = 4 # FIXME: or should it be 3?
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cmd_latency = 4
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# Commands read from adapters are delayed on ConstBitSlips
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# Commands read from adapters are delayed on ConstBitSlips
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ca_latency = 1
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ca_latency = 1
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@ -61,8 +61,7 @@ class DQSPattern(Module):
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self.comb += [
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self.comb += [
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self.o.eq(0b0101010101010101),
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self.o.eq(0b0101010101010101),
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If(self.preamble,
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If(self.preamble,
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# FIXME: using 2tCK write preamble, but it depends on mode registers
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self.o.eq(0b0101000001010101) # 2tCK write preamble
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self.o.eq(0b0101000001010101)
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),
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),
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If(self.postamble,
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If(self.postamble,
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self.o.eq(0b0101010101010100)
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self.o.eq(0b0101010101010100)
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