frontend/bist: replicate LFSR output to fill DRAM port
Signed-off-by: Michal Sieron <msieron@antmicro.com>
This commit is contained in:
parent
89581c1da7
commit
f466c5f1db
|
@ -8,6 +8,7 @@
|
||||||
"""Built In Self Test (BIST) modules for testing LiteDRAM functionality."""
|
"""Built In Self Test (BIST) modules for testing LiteDRAM functionality."""
|
||||||
|
|
||||||
from functools import reduce
|
from functools import reduce
|
||||||
|
from math import ceil
|
||||||
from operator import xor
|
from operator import xor
|
||||||
|
|
||||||
from migen import *
|
from migen import *
|
||||||
|
@ -211,7 +212,12 @@ class _LiteDRAMBISTGenerator(Module):
|
||||||
raise NotImplementedError
|
raise NotImplementedError
|
||||||
|
|
||||||
self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
|
self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
|
||||||
self.comb += dma.sink.data.eq(data_gen.o)
|
self.comb += dma.sink.data.eq(
|
||||||
|
Replicate(
|
||||||
|
data_gen.o,
|
||||||
|
ceil(dram_port.data_width / len(data_gen.o)),
|
||||||
|
)[:dram_port.data_width],
|
||||||
|
)
|
||||||
|
|
||||||
|
|
||||||
@ResetInserter()
|
@ResetInserter()
|
||||||
|
@ -511,7 +517,10 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
|
||||||
If(dma.source.valid,
|
If(dma.source.valid,
|
||||||
data_gen.ce.eq(1),
|
data_gen.ce.eq(1),
|
||||||
NextValue(data_counter, data_counter + 1),
|
NextValue(data_counter, data_counter + 1),
|
||||||
If(dma.source.data != data_gen.o[:min(len(data_gen.o), dram_port.data_width)],
|
If(dma.source.data != Replicate(
|
||||||
|
data_gen.o,
|
||||||
|
ceil(dram_port.data_width / len(data_gen.o)),
|
||||||
|
)[:dram_port.data_width],
|
||||||
NextValue(self.errors, self.errors + 1)
|
NextValue(self.errors, self.errors + 1)
|
||||||
),
|
),
|
||||||
If(data_counter == (self.length[ashift:] - 1),
|
If(data_counter == (self.length[ashift:] - 1),
|
||||||
|
|
Loading…
Reference in New Issue