litedram_gen: use default settings on wb_bus.

2020-05-13 14:50:06 +02:00 · 2020-05-13 14:50:06 +02:00 · f4871b9f13
parent 6fb8396d8e
commit f4871b9f13
1 changed files with 1 additions and 1 deletions
--- a/litedram/gen.py
+++ b/litedram/gen.py
@ -376,7 +376,7 @@ class LiteDRAMCore(SoCCore):
        self.comb += platform.request("init_error").eq(self.ddrctrl.init_error.storage)
        # If no CPU, expose a bus control interface to user.
        if cpu_type is None:
-            wb_bus = wishbone.Interface(self.bus.address_width)
+            wb_bus = wishbone.Interface()
            self.bus.add_master(master=wb_bus)
            platform.add_extension(wb_bus.get_ios("wb_ctrl"))
            wb_pads = platform.request("wb_ctrl")