phy/ecp5ddrphy: reorder signals/parameters on primitives
This commit is contained in:
Florent Kermarrec
parent
e0966e2ed3
commit
f4de17b8e6
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@ -142,37 +142,37 @@ class ECP5DDRPHY(Module, AutoCSR):
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for i in range(len(pads.clk_p)):
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sd_clk_se = Signal()
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = 0,
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i_D1 = 1,
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i_D2 = 0,
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i_D3 = 1,
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_RST = ResetSignal("sys2x"),
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o_Q = pads.clk_p[i]
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)
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# Addresses and Commands -------------------------------------------------------------------
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for i in range(addressbits):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = dfi.phases[0].address[i],
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i_D1 = dfi.phases[0].address[i],
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i_D2 = dfi.phases[1].address[i],
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i_D3 = dfi.phases[1].address[i],
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_RST = ResetSignal("sys2x"),
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o_Q = pads.a[i]
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)
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for i in range(bankbits):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = dfi.phases[0].bank[i],
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i_D1 = dfi.phases[0].bank[i],
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i_D2 = dfi.phases[1].bank[i],
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i_D3 = dfi.phases[1].bank[i],
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_RST = ResetSignal("sys2x"),
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o_Q = pads.ba[i]
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)
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controls = ["ras_n", "cas_n", "we_n", "cke", "odt"]
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@ -183,13 +183,13 @@ class ECP5DDRPHY(Module, AutoCSR):
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for name in controls:
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for i in range(len(getattr(pads, name))):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = getattr(dfi.phases[0], name)[i],
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i_D1 = getattr(dfi.phases[0], name)[i],
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i_D2 = getattr(dfi.phases[1], name)[i],
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i_D3 = getattr(dfi.phases[1], name)[i],
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_RST = ResetSignal("sys2x"),
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o_Q = getattr(pads, name)[i]
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)
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@ -289,14 +289,14 @@ class ECP5DDRPHY(Module, AutoCSR):
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dm_o_data_muxed.eq(dm_o_data[:4])
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)
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self.specials += Instance("ODDRX2DQA",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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i_D0 = dm_o_data_muxed[0],
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i_D1 = dm_o_data_muxed[1],
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i_D2 = dm_o_data_muxed[2],
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i_D3 = dm_o_data_muxed[3],
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i_RST = ResetSignal("sys2x"),
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i_DQSW270 = dqsw270,
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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o_Q = pads.dm[i]
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)
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@ -304,24 +304,24 @@ class ECP5DDRPHY(Module, AutoCSR):
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dqs_oe_n = Signal()
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self.specials += [
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Instance("ODDRX2DQSB",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW = dqsw,
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i_D0 = dqs_serdes_pattern[0],
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i_D1 = dqs_serdes_pattern[1],
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i_D2 = dqs_serdes_pattern[2],
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i_D3 = dqs_serdes_pattern[3],
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i_RST = ResetSignal("sys2x"),
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i_DQSW = dqsw,
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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o_Q = dqs
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),
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Instance("TSHX2DQSA",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW = dqsw,
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i_T0 = ~(oe_dqs|dqs_postamble),
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i_T1 = ~(oe_dqs|dqs_preamble),
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i_SCLK = ClockSignal(),
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i_ECLK = ClockSignal("sys2x"),
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i_DQSW = dqsw,
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i_RST = ResetSignal("sys2x"),
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o_Q = dqs_oe_n,
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o_Q = dqs_oe_n
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),
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Tristate(pads.dqs_p[i], dqs, ~dqs_oe_n, dqs_i)
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]
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@ -350,36 +350,36 @@ class ECP5DDRPHY(Module, AutoCSR):
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)
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self.specials += [
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Instance("ODDRX2DQA",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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i_D0 = dq_o_data_muxed[0],
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i_D1 = dq_o_data_muxed[1],
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i_D2 = dq_o_data_muxed[2],
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i_D3 = dq_o_data_muxed[3],
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i_RST = ResetSignal("sys2x"),
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i_DQSW270 = dqsw270,
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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o_Q = dq_o
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),
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Instance("DELAYF",
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i_A = dq_i,
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p_DEL_MODE = "DQS_ALIGNED_X2",
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i_LOADN = 1,
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i_MOVE = 0,
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i_DIRECTION = 0,
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o_Z = dq_i_delayed,
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p_DEL_MODE = "DQS_ALIGNED_X2"
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i_A = dq_i,
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o_Z = dq_i_delayed
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),
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Instance("IDDRX2DQA",
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i_D = dq_i_delayed,
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i_RST = ResetSignal("sys2x"),
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i_DQSR90 = dqsr90,
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i_SCLK = ClockSignal(),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSR90 = dqsr90,
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i_RDPNTR0 = rdpntr[0],
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i_RDPNTR1 = rdpntr[1],
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i_RDPNTR2 = rdpntr[2],
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i_WRPNTR0 = wrpntr[0],
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i_WRPNTR1 = wrpntr[1],
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i_WRPNTR2 = wrpntr[2],
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i_D = dq_i_delayed,
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o_Q0 = dq_i_data[0],
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o_Q1 = dq_i_data[1],
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o_Q2 = dq_i_data[2],
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@ -407,12 +407,12 @@ class ECP5DDRPHY(Module, AutoCSR):
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]
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self.specials += [
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Instance("TSHX2DQA",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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i_T0 = ~oe_dq,
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i_T1 = ~oe_dq,
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i_SCLK = ClockSignal(),
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i_ECLK = ClockSignal("sys2x"),
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i_DQSW270 = dqsw270,
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i_RST = ResetSignal("sys2x"),
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o_Q = dq_oe_n,
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),
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Tristate(pads.dq[j], dq_o, ~dq_oe_n, dq_i)
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