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frontend: add flush signal on dram ports and fix a specific case in LiteDRAMReadPortUpConverter

This commit is contained in:
Florent Kermarrec 2016-12-15 19:07:43 +01:00
parent bd40268961
commit f57dfad6a4
2 changed files with 5 additions and 1 deletions
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2
litedram/common.py
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@ -101,6 +101,8 @@ class LiteDRAMPort:
self.wdata = stream.Endpoint(wdata_description(dw))
self.rdata = stream.Endpoint(rdata_description(dw))
self.flush = Signal()
class LiteDRAMWritePort(LiteDRAMPort):
def __init__(self, *args, **kwargs):

4
litedram/frontend/adaptation.py
View File

@ -267,7 +267,9 @@ class LiteDRAMReadPortUpConverter(Module):
port_to.rdata.connect(rdata_buffer.sink),
rdata_buffer.source.connect(rdata_converter.sink),
rdata_chunk_valid.eq((cmd_buffer.source.sel & rdata_chunk) != 0),
If(cmd_buffer.source.valid,
If(port_from.flush,
rdata_converter.source.ready.eq(1)
).Elif(cmd_buffer.source.valid,
If(rdata_chunk_valid,
port_from.rdata.valid.eq(rdata_converter.source.valid),
port_from.rdata.data.eq(rdata_converter.source.data),