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lpddr5: sim: add write leveling step as well 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-09-15 12:54:48 +02:00
parent d7e2c82795
commit f8ac00a8ab
1 changed files with 11 additions and 1 deletions
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12
litedram/phy/lpddr5/simphy.py
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@ -51,10 +51,20 @@ class LPDDR5SimPHY(SimSerDesMixin, LPDDR5PHY):
# fake delays (make no nsense in simulation, but sdram.c expects them) # fake delays (make no nsense in simulation, but sdram.c expects them)
self.settings.read_leveling = True self.settings.read_leveling = True
self.settings.delays = 1
self._rdly_dq_rst = CSR() self._rdly_dq_rst = CSR()
self._rdly_dq_inc = CSR() self._rdly_dq_inc = CSR()
self.settings.write_leveling = True
self._cdly_rst = CSR()
self._cdly_inc = CSR()
self._wdly_dq_rst = CSR()
self._wdly_dq_inc = CSR()
self._wdly_dqs_rst = CSR()
self._wdly_dqs_inc = CSR()
self._half_sys8x_taps = CSR()
self.settings.delays = 1
delay = lambda sig, cycles: delayed(self, sig, cycles=cycles) delay = lambda sig, cycles: delayed(self, sig, cycles=cycles)
ddr_ck = dict(clkdiv="sys", clk="sys2x") ddr_ck = dict(clkdiv="sys", clk="sys2x")
ddr_ca = dict(clkdiv="sys", clk="sys4x") ddr_ca = dict(clkdiv="sys", clk="sys4x")