phy/model: simulate write latency
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@ -196,13 +196,15 @@ class SDRAMPHYModel(Module):
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self.comb += Case(precharges, cases)
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# Bank writes
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bank_write = Signal()
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bank_write_col = Signal(max=ncols)
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writes = Signal(len(phases))
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cases = {}
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for np, phase in enumerate(phases):
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self.comb += writes[np].eq(phase.write)
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cases[2**np] = [
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bank.write.eq(phase.bank == nb),
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bank.write_col.eq(phase.address)
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bank_write.eq(phase.bank == nb),
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bank_write_col.eq(phase.address)
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]
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self.comb += Case(writes, cases)
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self.comb += [
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@ -210,6 +212,22 @@ class SDRAMPHYModel(Module):
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bank.write_mask.eq(Cat(*[phase.wrdata_mask for phase in phases]))
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]
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# Simulate write latency
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for i in range(self.settings.write_latency):
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new_bank_write = Signal()
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new_bank_write_col = Signal(max=ncols)
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self.sync += [
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new_bank_write.eq(bank_write),
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new_bank_write_col.eq(bank_write_col)
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]
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bank_write = new_bank_write
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bank_write_col = new_bank_write_col
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self.comb += [
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bank.write.eq(bank_write),
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bank.write_col.eq(bank_write_col)
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]
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# Bank reads
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reads = Signal(len(phases))
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cases = {}
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