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Use the ready signal for cas_allowed so that arbitrators know not to iterate
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parent
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commit
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2 changed files with 13 additions and 17 deletions
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@ -32,7 +32,6 @@ class BankMachine(Module):
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self.refresh_req = Signal()
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self.refresh_gnt = Signal()
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self.ras_allowed = ras_allowed = Signal()
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self.cas_allowed = cas_allowed = Signal()
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a = settings.geom.addressbits
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ba = settings.geom.bankbits + log2_int(nranks)
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self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(a, ba))
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@ -108,20 +107,18 @@ class BankMachine(Module):
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).Elif(cmd_buffer.source.valid,
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If(has_openrow,
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If(hit,
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If(cas_allowed,
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cmd.valid.eq(1),
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If(cmd_buffer.source.we,
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req.wdata_ready.eq(cmd.ready),
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cmd.is_write.eq(1),
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cmd.we.eq(1),
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).Else(
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req.rdata_valid.eq(cmd.ready),
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cmd.is_read.eq(1)
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),
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cmd.cas.eq(1),
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If(cmd.ready & auto_precharge,
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NextState("AUTOPRECHARGE")
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)
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cmd.valid.eq(1),
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If(cmd_buffer.source.we,
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req.wdata_ready.eq(cmd.ready),
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cmd.is_write.eq(1),
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cmd.we.eq(1),
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).Else(
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req.rdata_valid.eq(cmd.ready),
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cmd.is_read.eq(1)
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),
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cmd.cas.eq(1),
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If(cmd.ready & auto_precharge,
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NextState("AUTOPRECHARGE")
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)
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).Else(
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NextState("PRECHARGE")
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@ -226,7 +226,6 @@ class Multiplexer(Module, AutoCSR):
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# CAS control
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self.comb += cas_allowed.eq(tccdcon.ready)
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self.comb += [bm.cas_allowed.eq(cas_allowed) for bm in bank_machines]
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# tWTR timing (Write to Read delay)
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self.submodules.twtrcon = twtrcon = tXXDController(
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@ -306,7 +305,7 @@ class Multiplexer(Module, AutoCSR):
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choose_req.want_reads.eq(1),
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choose_cmd.want_activates.eq(ras_allowed),
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choose_cmd.cmd.ready.eq(~choose_cmd.activate() | ras_allowed),
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choose_req.cmd.ready.eq(1),
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choose_req.cmd.ready.eq(cas_allowed),
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steerer_sel(steerer, "read"),
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If(write_available,
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# TODO: switch only after several cycles of ~read_available?
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