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Use the ready signal for cas_allowed so that arbitrators know not to iterate

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This commit is contained in:
John Sully 2018-09-22 17:15:19 +02:00
parent c12404e00c
commit fa0f3b2777
2 changed files with 13 additions and 17 deletions
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3
litedram/core/bankmachine.py
View file

@ -32,7 +32,6 @@ class BankMachine(Module):
self.refresh_req = Signal()
self.refresh_gnt = Signal()
self.ras_allowed = ras_allowed = Signal()
self.cas_allowed = cas_allowed = Signal()
a = settings.geom.addressbits
ba = settings.geom.bankbits + log2_int(nranks)
self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(a, ba))
@ -108,7 +107,6 @@ class BankMachine(Module):
).Elif(cmd_buffer.source.valid,
If(has_openrow,
If(hit,
If(cas_allowed,
cmd.valid.eq(1),
If(cmd_buffer.source.we,
req.wdata_ready.eq(cmd.ready),
@ -122,7 +120,6 @@ class BankMachine(Module):
If(cmd.ready & auto_precharge,
NextState("AUTOPRECHARGE")
)
)
).Else(
NextState("PRECHARGE")
)

3
litedram/core/multiplexer.py
View file

@ -226,7 +226,6 @@ class Multiplexer(Module, AutoCSR):
# CAS control
self.comb += cas_allowed.eq(tccdcon.ready)
self.comb += [bm.cas_allowed.eq(cas_allowed) for bm in bank_machines]
# tWTR timing (Write to Read delay)
self.submodules.twtrcon = twtrcon = tXXDController(
@ -306,7 +305,7 @@ class Multiplexer(Module, AutoCSR):
choose_req.want_reads.eq(1),
choose_cmd.want_activates.eq(ras_allowed),
choose_cmd.cmd.ready.eq(~choose_cmd.activate() | ras_allowed),
choose_req.cmd.ready.eq(1),
choose_req.cmd.ready.eq(cas_allowed),
steerer_sel(steerer, "read"),
If(write_available,
# TODO: switch only after several cycles of ~read_available?