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modules: make IS43TR16128B consistent with others SDRAMModules

This commit is contained in:
Florent Kermarrec 2019-05-28 10:02:02 +02:00
parent 02448a3670
commit fbd7ae3e62
1 changed files with 3 additions and 2 deletions
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5
litedram/modules.py
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@ -310,7 +310,7 @@ class K4B2G1646F(SDRAMModule):
speedgrade_timings["default"] = speedgrade_timings["1600"]
class IS43TR16128B_125K(SDRAMModule):
class IS43TR16128B(SDRAMModule):
memtype = "DDR3"
# geometry
nbanks = 8
@ -319,8 +319,9 @@ class IS43TR16128B_125K(SDRAMModule):
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6))
speedgrade_timings = {
"default": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=160, tFAW=(None, 40), tRAS=35),
"1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=160, tFAW=(None, 40), tRAS=35),
}
speedgrade_timings["default"] = speedgrade_timings["1600"]
# DDR3 (SO-DIMM)