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Merge pull request #244 from antmicro/jboc/dq-dqs-training 

Add DQ-DQS training for LPDDR4 PHY
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enjoy-digital 2021-04-22 17:28:10 +02:00 committed by GitHub
parent 6256031d51 ebaf63479d
commit fda8689142
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1 changed files with 4 additions and 1 deletions
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litedram/init.py
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@ -456,6 +456,7 @@ def get_lpddr4_phy_init_sequence(phy_settings, timing_settings):
bl = 16 bl = 16
dq_odt = "RZQ/2" dq_odt = "RZQ/2"
ca_odt = "RZQ/2" ca_odt = "RZQ/2"
pull_down_drive_strength = "RZQ/3"
def get_nwr(): def get_nwr():
frequency_ranges = [ # Table 28. Frequency Ranges for RL, WL, nWR, and nRTP Settings frequency_ranges = [ # Table 28. Frequency Ranges for RL, WL, nWR, and nRTP Settings
@ -575,7 +576,7 @@ def get_lpddr4_phy_init_sequence(phy_settings, timing_settings):
(0, 1, 1), (0, 1, 1),
(1, 1, 0), (1, 1, 0),
(2, 1, 0), (2, 1, 0),
(3, 3, odt_map["RZQ/6"]), (3, 3, odt_map[pull_down_drive_strength]),
(6, 1, 0), (6, 1, 0),
(7, 1, 0), (7, 1, 0),
]) ])
@ -690,6 +691,8 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
'K7LPDDR4PHY', 'V7LPDDR4PHY']: 'K7LPDDR4PHY', 'V7LPDDR4PHY']:
r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n" r += "#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE\n"
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
if phytype in ['K7LPDDR4PHY', 'V7LPDDR4PHY']:
r += "#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE\n"
if phytype in ["ECP5DDRPHY"]: if phytype in ["ECP5DDRPHY"]:
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n" r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
if phytype in ["LPDDR4SIMPHY"]: if phytype in ["LPDDR4SIMPHY"]: