litedram_gen: Fix error with --sim option

It looks like commit 317072a198 ("litedram_gen: Add initial SDRAM support (with ULX3S example)") broke building with the --sim option.
2021-08-09 10:35:17 +10:00 · 2021-08-09 10:35:17 +10:00 · fe1bb083ef
parent ae139096c0
commit fe1bb083ef
1 changed files with 1 additions and 1 deletions
--- a/litedram/gen.py
+++ b/litedram/gen.py
@ -501,7 +501,7 @@ class LiteDRAMCore(SoCCore):
                memtype    = sdram_module.memtype,
                data_width = core_config["sdram_module_nb"]*8,
                clk_freq   = sdram_clk_freq)
-            self.submodules.ddrphy = SDRAMPHYModel(
+            self.submodules.ddrphy = sdram_phy = SDRAMPHYModel(
                module    = sdram_module,
                settings  = phy_settings,
                clk_freq  = sdram_clk_freq)