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5 Commits

Author SHA1 Message Date
Florent Kermarrec ac33d29727 litedram_gen: simplify and expose bus when CPU is set to None. 2020-05-12 09:07:59 +02:00
Florent Kermarrec fe478382e1 litedram_gen: expose a Bus Slave port instead of a CSR port. 
The logic overhead is minimal and it makes things easier with more flexibility:
- since the main Bus is arbitrated, CPU and Bus Slave can coexist.
- integration is easier in LiteX.
- bridging to APB/AXI is easier.
 2020-05-11 22:47:09 +02:00
Florent Kermarrec e5e4f528d4 examples/versa_ecp5.yml: enable CPU (required for DDR3 calibration), update copyright 2020-01-27 18:30:24 +01:00
Florent Kermarrec 4d19620a37 litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY) 2020-01-27 18:20:16 +01:00
Stefan Schrijvers 340a796129
litedram_gen: add ecp5 support 2020-01-25 18:59:26 +01:00