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1,170 Commits 5 Branches 14 Tags 5.7 MiB
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8 Commits

Author SHA1 Message Date
Jędrzej Boczar 5c6796b92a lpddr4: change MRW command encoding to avoid changing BIOS code 2021-03-25 15:30:48 +01:00
Jędrzej Boczar eb1d900c24 lpddr4: S7PHY related fixes, MRR command, runtime configurable WRITE/MASKED-WRITE 2021-03-25 15:29:17 +01:00
Jędrzej Boczar 4415a3eaf5 lpddr4: improve simulation and Verilator tests runner 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 2ab763ac5e lpddr4: add double-rate PHY, clean up and improve PHY implementation 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 183f1643aa lpddr4: add support for MASKED-WRITE 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 05ed238829 lpddr4: split implementation into multiple files in separate directory 2021-03-25 15:19:16 +01:00
Jędrzej Boczar ee9c2b4cf7 lpddr4: implement ZQC through MPC and include it in init sequence 
We do not yet support ZQC during operation (after init sequence)
as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between,
which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 6943a1a4a5 lpddr4: initial PHY logic and simulation tests 2021-03-25 15:19:08 +01:00