Commit Graph

3 Commits

Author SHA1 Message Date
Maciej Dudek 7b3c6abd50 litedram/frontend/adapter.py rewrite up converter to optimize for bandwidth
This change is necessary to run litevideo, as old up converter was too slow to support
high bandwidth requirements of HDMI core.
Also old upconverter had two bugs:
* reading sequentially and non-sequentially would return data in the same order
* writing sequentailly and non-sequentially would return different memory state

test/test_adapter.py add new up converter test: test_up_converter_writes_not_sequential
This test checks if non-sequential writes to one dram word will create the same result as sequential writes
Add parameters for rx_buffer, tx_buffer and cmd_buffer depths

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2022-06-27 17:49:31 +02:00
Florent Kermarrec ac825e5112 add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
Florent Kermarrec 16fd46bf35 frontend: rename adaptation to adapter. 2020-08-05 11:10:42 +02:00