Commit Graph

1444 Commits

Author SHA1 Message Date
Maciej Dudek c54fc4af82 Fix UpConverter write path not working as intended
LiteDRAM controler does not check if wdata stream has valid signal set,
it assumes that wdata has valid data when cmd is send.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2022-06-27 17:49:31 +02:00
Maciej Dudek 7b3c6abd50 litedram/frontend/adapter.py rewrite up converter to optimize for bandwidth
This change is necessary to run litevideo, as old up converter was too slow to support
high bandwidth requirements of HDMI core.
Also old upconverter had two bugs:
* reading sequentially and non-sequentially would return data in the same order
* writing sequentailly and non-sequentially would return different memory state

test/test_adapter.py add new up converter test: test_up_converter_writes_not_sequential
This test checks if non-sequential writes to one dram word will create the same result as sequential writes
Add parameters for rx_buffer, tx_buffer and cmd_buffer depths

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2022-06-27 17:49:31 +02:00
Florent Kermarrec 3d066c87f9 ci: Add comment for Verilator build/install. 2022-06-27 17:46:37 +02:00
Florent Kermarrec e662fadf8a test/test_init: Update. 2022-05-10 10:38:55 +02:00
Florent Kermarrec 85e4c995d8 litedram/gen: .init renaming no longer required with https://github.com/enjoy-digital/litex/pull/1293. 2022-05-09 18:02:57 +02:00
Florent Kermarrec 2b8af870c5 phy/usddrphy/Clk: Connect cdly_value only on first clk pad. 2022-05-02 17:34:52 +02:00
Florent Kermarrec 692355d120 CONTRIBUTORS: Update. 2022-05-02 13:43:38 +02:00
Florent Kermarrec 745f2a060a bench/targets: Use full imports. 2022-05-02 13:07:29 +02:00
Florent Kermarrec 47ddb03ec8 phy/rpc/arty: Use new I2C init to automatically inialize Vbucks and integrate modified DDR3 IOs (SSTL15). 2022-04-29 14:16:47 +02:00
Florent Kermarrec b313fe5224 phy/rpc/arty: Remove calls to add_csrs (No longer required) and fix build. 2022-04-29 13:13:38 +02:00
Florent Kermarrec 9e0d5ca22d phy/rpc: Add Arty target file that has used to validate RPC-DRAM. 2022-04-29 13:10:22 +02:00
Florent Kermarrec f396253729 frontend/axi/rmw: Fix simulation mismatch between unit-test/verilator. 2022-04-11 17:49:19 +02:00
Florent Kermarrec 15f7ba2713 frontend/adapter: Set with_common_rst to False on ClockDomainCrossing. 2022-04-01 11:46:43 +02:00
enjoy-digital 000c220a57
Merge pull request #300 from antmicro/variable_dq_dqs_ratio
Allow for variable DQ/DQS ratio
2022-03-31 17:21:01 +02:00
Ryszard Różak 18d25d84c3 Update test/reference/*_init.h
Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
2022-03-30 13:42:47 +02:00
Karol Gugala 574df6f908 Allow for variable DQ/DQS ratio
Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
2022-03-30 13:42:47 +02:00
Florent Kermarrec b404a7f0f2 dfii: Improve hardware/software control comments. 2022-03-28 14:27:41 +02:00
enjoy-digital c396e3f153
Merge pull request #302 from antmicro/external-dfi-injector
dfi: add possibility to have an external dfi injector
2022-03-28 14:22:31 +02:00
enjoy-digital 27939f2d0b
Merge pull request #301 from Johnsel/arduino_mkrvidor4000
Added AS4C4M16 for Arduino MKR Vidor 4000 support
2022-03-28 14:16:38 +02:00
Jędrzej Boczar 7e30fda871 Add DFIInjector CSRs documentation 2022-03-28 10:09:43 +02:00
Florent Kermarrec 05d3be476c phy/ecp5ddrphy: Reduce rdly to 3-bit. 2022-03-22 17:08:51 +01:00
John Simons f14577a147 Added AS4C4M16 residing on Arduino MKR Vidor 4000 2022-03-21 18:56:57 -07:00
Jędrzej Boczar da2748723d Add option to switch DFIInjector to externally driven DFI 2022-03-07 11:21:02 +01:00
Florent Kermarrec 4c1ce026e9 phy/s7ddrphy: Disable write_latency_calibration by default on Artix7 boards. 2022-03-03 15:29:32 +01:00
enjoy-digital c7d4d7f1b4
Merge pull request #295 from antmicro/acom/rdimm-phy-working
s7phy: fix DDR4 mode
2022-03-03 15:09:58 +01:00
Alessandro Comodi 27b11d755c init: ddr4: add inversion also in python init
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-02 14:33:51 +01:00
Alessandro Comodi 4eb5cd9c40 s7: fix DDR4 mode
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-01 13:40:13 +01:00
Florent Kermarrec af94e8497a litedram_gen: Enable Read-Modify-Write support with ECC. 2022-02-28 18:52:32 +01:00
Florent Kermarrec 095180be6a frontend/AXI: Add optional Read-Modify-Write mode for cases where w.strb is not available on the DRAM side (ex when ECC is enabled).
When enabled, partial writes are automatically detected and a Read-Modify-Write access is
done. Before doing a RMW access, pending accesses are terminated and incoming accesses are
stalled until RMW access is done.

Enable with_read_modify_write in test_axi.
2022-02-28 18:45:46 +01:00
Florent Kermarrec 81ae73b74a test/test_axi: Exercise w.strb through randomness (as we are doing for data). 2022-02-28 18:35:39 +01:00
Florent Kermarrec 3f84cc9116 ddr3_mr_gen: Also display RZQ/x on configured electrical settings. 2022-02-24 16:33:46 +01:00
Florent Kermarrec 70c1491d1c ddr3_mr_gen: Display RZQ/x with --list (Useful for comparison with MIG's settings expressed in RZQ/x). 2022-02-24 14:44:02 +01:00
Florent Kermarrec e48471ea43 phy/s7ddrphy: Expose write_latency_calibration parameter and revert it to True by default. 2022-02-23 10:36:42 +01:00
Florent Kermarrec a0580c7ae7 frontend/axi: Add Write Buffer reservation mechanisms to know when we have enough data in the buffer to generate the command. 2022-02-17 17:21:02 +01:00
Florent Kermarrec 963233aefb litedram_gen: Add ECC support on ports and add example on kcu105. 2022-02-16 11:34:36 +01:00
Florent Kermarrec 68c082bf20 frontend/axi: Only switch between read/write at the end of a burst. 2022-02-15 18:05:47 +01:00
Florent Kermarrec 497bbc0394 frontend/axi: Improve similarities in aw/ar handling. 2022-02-15 17:43:38 +01:00
Florent Kermarrec 72ca120fa0 frontend/axi/LiteDRAMAXI2NativeW: Decouple axi.w from axi.aw and allow buffering in w_buffer without waiting for cmd to be accepted. 2022-02-15 17:34:09 +01:00
Florent Kermarrec 5f722a1513 bench/test: Avoid use of ident_version (should fix CI). 2022-02-15 17:33:31 +01:00
Florent Kermarrec e6758539d9 litedram_gen: Minor cosmetic cleanup. 2022-02-08 18:28:57 +01:00
Florent Kermarrec 24fad45764 frontend/dma/LiteDRAMDMAReader: Make sure to flush FIFO/Reservation counter when disabled. 2022-01-17 10:56:09 +01:00
Florent Kermarrec 62abf9ce0c litedram_gen: Add block_until_ready port parameter to control blocking behaviour.
In some cases, blocking the port until controller is ready is not wanted (ex on No-CPU
config where a port is used for the memtest).
2022-01-13 21:51:57 +01:00
Florent Kermarrec 2d47363f46 test/benchmark: Switch from soc_sdram (deprecated) to soc_core. 2022-01-07 18:37:13 +01:00
Florent Kermarrec e5e3b6c9a3 phy/s7ddrphy: Only do write latency calibration on Kintex7/Virtex7.
This has been causing issues on Artix7 and is only required with write_leveling.
2022-01-07 11:59:59 +01:00
Florent Kermarrec 1b0545cd60 Bump year. 2022-01-05 09:01:50 +01:00
enjoy-digital 6c0fe3ab6e
Merge pull request #290 from tongchen126/master
add support for MT41K256M8 module
2021-12-27 12:40:12 +01:00
tongchen126 15929e109d add support for MT41K256M8 module 2021-12-20 11:52:11 +08:00
Florent Kermarrec 17c19de8f8 frontend/dma: Move ack of write responses and other cosmetic cleanups. 2021-11-29 13:22:56 +01:00
enjoy-digital 925dbfd933
Merge pull request #286 from mkj/matt/orangecrab
litedram_gen fixes for ECP5
2021-11-29 08:36:11 +01:00
enjoy-digital 5b233742a4
Merge pull request #287 from cklarhorst/master
add LPDDR module
2021-11-29 08:34:21 +01:00