Hardware/litedram
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320 commits 5 branches 14 tags 5.7 MiB
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5 commits

Author SHA1 Message Date
Florent Kermarrec
95cb7cdba5 test: rename read/write generators to handlers 2018-08-28 13:40:50 +02:00
Florent Kermarrec
2b20c11e2d add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
 2018-08-21 13:21:04 +02:00
Florent Kermarrec
c28a754867 test: update 2018-08-09 10:54:42 +02:00
Florent Kermarrec
697f46a97f replace litex.gen imports with migen imports 2018-02-23 13:39:23 +01:00
Florent Kermarrec
ad304c8997 test: convert to python unittests and some cleanup 2017-01-17 13:18:11 +01:00