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litedram/examples
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Hans Baier f1293eae1e
Avalon frontend for LiteDRAM (#337) 
Add initial Avalon MM frontend + tests.
2023-05-23 14:52:05 +02:00
..
arty.yml Avalon frontend for LiteDRAM (#337) 2023-05-23 14:52:05 +02:00
genesys2.yml litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 2021-09-16 17:01:00 +02:00
kcu105.yml litedram_gen: Add ECC support on ports and add example on kcu105. 2022-02-16 11:34:36 +01:00
nexys4ddr.yml litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 2021-09-16 17:01:00 +02:00
ulx3s.yml litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 2021-09-16 17:01:00 +02:00
versa_ecp5.yml examples/versa_ecp5: Fix memtype. 2021-10-07 13:44:36 +02:00
xcu1525.yml litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 2021-09-16 17:01:00 +02:00