f1293eae1e
Avalon frontend for LiteDRAM ( #337 )
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Add initial Avalon MM frontend + tests.
2023-05-23 14:52:05 +02:00
963233aefb
litedram_gen: Add ECC support on ports and add example on kcu105.
2022-02-16 11:34:36 +01:00
62abf9ce0c
litedram_gen: Add block_until_ready port parameter to control blocking behaviour.
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In some cases, blocking the port until controller is ready is not wanted (ex on No-CPU
config where a port is used for the memtest).
2022-01-13 21:51:57 +01:00
ba0012f881
examples/versa_ecp5: Fix memtype.
2021-10-07 13:44:36 +02:00
e0e204a514
litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart).
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It's more interesting in some design to access the UART through a FIFO like
interface than through RS232.
2021-09-16 17:01:00 +02:00
a11d1b870d
litedram_gen: Remove device limitation on GENSDRPHY/ECP5DDRPHY.
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By specifying FPGA device in .yml files for configs requiring it.
2021-07-02 09:15:42 +02:00
317072a198
litedram_gen: Add initial SDRAM support (with ULX3S example).
2021-07-02 09:01:31 +02:00
ab2423e3dd
litedram_gen: add initial Ultrascale+ support with XCU1525 .yml example.
2021-01-22 12:04:24 +01:00
ac825e5112
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
4e62d28af6
examples/.yml: set cmd_latency to 1 on Kintex7/Ultrascale (values valided in LiteX-Boards).
2020-08-06 11:52:34 +02:00
992f80c68b
litedram_gen: add Ultrascale(+) support and KCU105 config file, remove cmd_delay on 7-series (not automatically calibrated).
2020-06-03 09:35:40 +02:00
ac33d29727
litedram_gen: simplify and expose bus when CPU is set to None.
2020-05-12 09:07:59 +02:00
fe478382e1
litedram_gen: expose a Bus Slave port instead of a CSR port.
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The logic overhead is minimal and it makes things easier with more flexibility:
- since the main Bus is arbitrated, CPU and Bus Slave can coexist.
- integration is easier in LiteX.
- bridging to APB/AXI is easier.
2020-05-11 22:47:09 +02:00
e5e4f528d4
examples/versa_ecp5.yml: enable CPU (required for DDR3 calibration), update copyright
2020-01-27 18:30:24 +01:00
4d19620a37
litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY)
2020-01-27 18:20:16 +01:00
340a796129
litedram_gen: add ecp5 support
2020-01-25 18:59:26 +01:00
61b19e2aaf
litedram_gen: improve flexibility to define user ports
2020-01-15 12:57:33 +01:00
76caff5417
litedram_gen: add initial FIFO support
2020-01-14 18:19:32 +01:00
db97203877
gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore
2019-09-23 12:55:14 +02:00
233191939e
gen: change CSR config names, switch to csr_expose/csr_align
2019-09-23 09:12:40 +02:00
d37a30e0d7
litedram_gen: add wishbone user port support
2019-09-03 23:47:08 +02:00
2bdeda021b
move standalone core generation to litedram package and make it usable externally
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When LiteDRAM is installed, standalone core can now be generated with "litedram_gen config.yml"
2019-08-28 07:19:30 +02:00
0dde125740
examples/litedram_gen: fix #!/usr/bin/env python3 location
2019-08-28 07:09:58 +02:00
602ff8be81
examples: switch to YAML config files
2019-08-28 07:08:10 +02:00
f018c9e268
add CONTRIBUTORS file and add copyright header to all files.
2019-06-23 23:59:10 +02:00
65451f426a
examples/litedram_gen: allow direct access to CSR (I/O) registers
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
[florent@enjoy-digital.fr: use add_csr_master, fix csr_port.dat_r typo]
2019-05-16 15:05:30 -04:00
b93412bbdc
examples: remove verilog simulation
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Simulation was here just to show how to do system level simulation adn required
external component to work (stadalone init).
2019-05-10 13:05:48 +02:00
a7e46bb25c
example/litedram_gen: reserve_nmi_interrupt no longer exists
2019-05-10 12:43:23 +02:00
c4161cfbfe
examples: update sim
2019-03-15 20:16:42 +01:00
640194a5c9
examples: add nexys4ddr_config
2019-02-21 23:32:45 +01:00
0ac1af367a
examples/litedram_gen: add DDR2 support
2019-02-21 23:32:23 +01:00
f4184ec37a
example/litedram_gen: update, add descriptions of config parameters
2019-02-21 23:19:52 +01:00
bc6a3f220a
examples/sim/sim/py: remove apb interface
2018-11-17 09:30:58 +01:00
e7e4bc527f
examples/sim: add ddr3 micron model
2018-11-17 09:20:34 +01:00
f219693635
examples: add simulation
2018-11-17 09:19:52 +01:00
f11506accd
examples/litedram_gen: cleanup pins definition
2018-10-15 09:38:34 +02:00
0f46dc4ab7
modules: add DDR3-800 timings for MT41J128M16 and use it on arty example
2018-10-01 11:59:54 +02:00
426ae23d2a
examples/litedram_gen: add sdram_module_speedgrade parameter
2018-10-01 11:48:15 +02:00
30c32f557c
example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :)
2018-09-25 10:40:24 +02:00
37f1decfb2
multirank: one cs_n/cke/odt/clk per rank
2018-09-09 14:32:15 +02:00
8ddc6c735d
drive odt of all ranks, fixes and test non regression with 1 rank
2018-09-09 01:52:24 +02:00
cc481be81f
examples: add sdram_rank_nb and user_ports_id_width
2018-09-07 17:55:46 +02:00
1652ab95c8
examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)
2018-09-05 09:13:47 +02:00
1e64b7f492
examples/litedram_gen: expose resp signals to user
2018-09-05 08:51:27 +02:00
de69867995
examples/litedram_gen: expose last signals to user
2018-09-05 08:32:49 +02:00
e8bd782999
examples/litedram_gen: expose burst signals to user
2018-09-05 08:31:57 +02:00
5e4dca9a7b
add examples with standalone cores for arty and genesys2
2018-08-31 23:20:47 +02:00
Hans Baier
Florent Kermarrec
Stefan Schrijvers
Gabriel L. Somlo