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examples/litedram_gen: add sdram_module_speedgrade parameter

This commit is contained in:
Florent Kermarrec 2018-10-01 11:48:15 +02:00
parent 1bc016cf6c
commit 426ae23d2a
3 changed files with 3 additions and 1 deletions
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1
examples/arty_config.py
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@ -8,6 +8,7 @@ core_config = {
# modules / phy
"sdram_module": MT41K128M16,
"sdram_module_nb": 1,
"sdram_module_speedgrade": "1066",
"sdram_rank_nb": 1,
"sdram_phy": A7DDRPHY,

1
examples/genesys2_config.py
View File

@ -8,6 +8,7 @@ core_config = {
# modules / phy
"sdram_module": MT41J256M16,
"sdram_module_nb": 2,
"sdram_module_speedgrade": "1333",
"sdram_rank_nb": 1,
"sdram_phy": K7DDRPHY,

2
examples/litedram_gen.py
View File

@ -210,7 +210,7 @@ class LiteDRAMCore(SoCSDRAM):
rtt_nom=core_config["rtt_nom"],
rtt_wr=core_config["rtt_wr"],
ron=core_config["ron"])
sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4")
sdram_module = core_config["sdram_module"](sys_clk_freq, "1:4", speedgrade=core_config["sdram_module_speedgrade"])
controller_settings = controller_settings=ControllerSettings(
cmd_buffer_depth=core_config["cmd_buffer_depth"],
read_time=core_config["read_time"],