Florent Kermarrec e70d77e76e phy/s7dddrphy: fix nphases = 2 (same code can be shared between nphases = 2 and nphases = 4)		2018-11-29 16:56:23 +01:00
..
core	core: make address_mapping a controller setting	2018-11-13 09:18:46 +01:00
frontend	frontend/wishbone: set aw/ar size on LiteDRAMWishbone2AXI	2018-11-26 10:37:28 +01:00
phy	phy/s7dddrphy: fix nphases = 2 (same code can be shared between nphases = 2 and nphases = 4)	2018-11-29 16:56:23 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common: add DDR4 burst_length	2018-11-05 10:46:34 +01:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	modules: add MT40A1G8 DDR4	2018-11-13 11:05:38 +01:00
sdram_init.py	sdram_init: fix compilation	2018-11-05 10:46:47 +01:00