376 lines
12 KiB
Python
376 lines
12 KiB
Python
# This file is Copyright (c) 2016-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2016 Tim 'mithro' Ansell <mithro@mithis.com>
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# License: BSD
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import unittest
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import random
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from migen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import *
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from litedram.frontend.bist import *
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from litedram.frontend.bist import _LiteDRAMBISTGenerator, _LiteDRAMBISTChecker, \
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_LiteDRAMPatternGenerator, _LiteDRAMPatternChecker
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from test.common import *
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from litex.gen.sim import *
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class GenCheckDriver:
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def __init__(self, module):
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self.module = module
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def reset(self):
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yield self.module.reset.eq(1)
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yield
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yield self.module.reset.eq(0)
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yield
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def configure(self, base, length, end=None):
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# for non-pattern generators/checkers
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if end is None:
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end = base + 0x100000
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yield self.module.base.eq(base)
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yield self.module.end.eq(end)
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yield self.module.length.eq(length)
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def run(self):
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yield self.module.run.eq(1)
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yield self.module.start.eq(1)
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yield
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yield self.module.start.eq(0)
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yield
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while((yield self.module.done) == 0):
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yield
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if hasattr(self.module, "errors"):
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self.errors = (yield self.module.errors)
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class TestBIST(unittest.TestCase):
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def test_generator(self):
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port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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def main_generator(dut):
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self.errors = 0
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# test incr
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yield dut.ce.eq(1)
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yield dut.random_enable.eq(0)
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yield
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for i in range(1024):
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data = (yield dut.o)
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if data != i:
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self.errors += 1
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yield
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# test random
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datas = []
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yield dut.ce.eq(1)
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yield dut.random_enable.eq(1)
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for i in range(1024):
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data = (yield dut.o)
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if data in datas:
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self.errors += 1
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datas.append(data)
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yield
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# dut
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dut = Generator(23, n_state=23, taps=[17, 22])
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# simulation
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generators = [main_generator(dut)]
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run_simulation(dut, generators)
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self.assertEqual(self.errors, 0)
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def bist_generator_test(self, data_width, base, length, end, mem_depth, init_generator=None):
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end_addr = base + length
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start_word = base // (data_width//8)
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end_word = end_addr // (data_width//8)
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n_words = end_word - start_word
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=data_width)
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self.submodules.generator = _LiteDRAMBISTGenerator(self.write_port)
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self.mem = DRAMMemory(data_width, mem_depth)
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def main_generator(dut):
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generator = GenCheckDriver(dut.generator)
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if init_generator is not None:
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yield from init_generator(dut)
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yield from generator.reset()
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yield from generator.configure(base, length, end=end)
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yield from generator.run()
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yield
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dut = DUT()
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generators = [
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main_generator(dut),
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dut.mem.write_handler(dut.write_port),
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]
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return dut, generators
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def test_bist_generator(self):
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dut, generators = self.bist_generator_test(mem_depth=128, data_width=32, end=128 * 4,
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base=16, length=64)
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run_simulation(dut, generators)
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before = 16 // 4
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mem_expected = [0] * before + list(range(64//4)) + [0] * (128 - 64//4 - before)
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self.assertEqual(dut.mem.mem, mem_expected)
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def test_bist_generator_random_data(self):
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def init(dut):
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yield dut.generator.random_data.eq(1)
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yield
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# fill whole memory
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dut, generators = self.bist_generator_test(mem_depth=128, data_width=32, end=128 * 4,
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base=0, length=128 * 4, init_generator=init)
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run_simulation(dut, generators)
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# only check if there are no duplicates and if data is not a simple sequence
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self.assertEqual(len(set(dut.mem.mem)), len(dut.mem.mem), msg='Duplicate values in memory')
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self.assertNotEqual(dut.mem.mem, list(range(128)), msg='Values are a sequence')
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def test_bist_generator_random_addr(self): # write whole memory and check if there are no repetitions?
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def init(dut):
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yield dut.generator.random_addr.eq(1)
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yield
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# fill whole memory
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dut, generators = self.bist_generator_test(mem_depth=128, data_width=32, end=128 * 4,
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base=0, length=128 * 4, init_generator=init)
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run_simulation(dut, generators)
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# with random address and address wrapping (generator.end) we _can_ have duplicates
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# we can at least check that the values written are not an ordered sequence
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self.assertNotEqual(dut.mem.mem, list(range(128)), msg='Values are a sequence')
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def test_bist_generator_wraps_addr(self):
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dut, generators = self.bist_generator_test(mem_depth=128, data_width=32,
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base=16, length=96, end=32)
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run_simulation(dut, generators)
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# we restrict address to <16, 32) and write 96 bytes (which results in 96/4=24 words generated)
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# this means that the address should wrap and last 8 generated words should overwrite memory
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# at address <16, 24)
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before = 16 // 4
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mem_expected = [0] * 4 + list(range(16)) + [0] * (128 - 4 - 16)
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mem_expected[4:4+8] = list(range(16, 24))
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self.assertEqual(dut.mem.mem, mem_expected)
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def pattern_generator_test(self, pattern, mem_expected, data_width, mem_depth):
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class DUT(Module):
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def __init__(self, init):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=data_width)
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self.submodules.generator = _LiteDRAMPatternGenerator(self.write_port, init=init)
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self.mem = DRAMMemory(data_width, mem_depth)
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def main_generator(dut):
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generator = GenCheckDriver(dut.generator)
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yield from generator.reset()
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yield from generator.run()
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yield
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dut = DUT(init=pattern)
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generators = [
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main_generator(dut),
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dut.mem.write_handler(dut.write_port),
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]
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run_simulation(dut, generators, vcd_name='/tmp/sim.vcd')
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assert len(mem_expected) == mem_depth
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self.assertEqual(dut.mem.mem, mem_expected)
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def test_pattern_generator_8bit(self):
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pattern = [
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# address, data
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(0x00, 0xaa),
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(0x05, 0xbb),
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(0x02, 0xcc),
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(0x07, 0xdd),
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]
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expected = [
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# data, address
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0xaa, # 0x00
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0x00, # 0x01
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0xcc, # 0x02
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0x00, # 0x03
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0x00, # 0x04
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0xbb, # 0x05
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0x00, # 0x06
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0xdd, # 0x07
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]
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self.pattern_generator_test(pattern, expected, data_width=8, mem_depth=8)
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def test_pattern_generator_64bit(self):
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pattern = [
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# address, data
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(0x00, 0x0ddf00dbadc0ffee),
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(0x05, 0xabadcafebaadf00d),
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(0x02, 0xcafefeedfeedface),
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(0x07, 0xdeadc0debaadbeef),
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]
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expected = [
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# data, address
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0x0ddf00dbadc0ffee, # 0x00
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0x0000000000000000, # 0x08
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0xcafefeedfeedface, # 0x10
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0x0000000000000000, # 0x18
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0x0000000000000000, # 0x20
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0xabadcafebaadf00d, # 0x28
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0x0000000000000000, # 0x30
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0xdeadc0debaadbeef, # 0x38
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]
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self.pattern_generator_test(pattern, expected, data_width=64, mem_depth=8)
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def test_pattern_generator_aligned(self):
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pattern = [
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# address, data
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(0x00, 0xabadcafe),
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(0x07, 0xbaadf00d),
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(0x02, 0xcafefeed),
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(0x01, 0xdeadc0de),
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]
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expected = [
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# data, address
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0xabadcafe, # 0x00
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0xdeadc0de, # 0x04
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0xcafefeed, # 0x08
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0x00000000, # 0x0c
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0x00000000, # 0x10
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0x00000000, # 0x14
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0x00000000, # 0x18
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0xbaadf00d, # 0x1c
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]
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self.pattern_generator_test(pattern, expected, data_width=32, mem_depth=8)
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def test_pattern_generator_not_aligned(self):
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pattern = [
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# address, data
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(0x00, 0xabadcafe),
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(0x07, 0xbaadf00d),
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(0x02, 0xcafefeed),
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(0x01, 0xdeadc0de),
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]
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expected = [
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# data, address
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0xabadcafe, # 0x00
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0xdeadc0de, # 0x04
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0xcafefeed, # 0x08
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0x00000000, # 0x0c
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0x00000000, # 0x10
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0x00000000, # 0x14
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0x00000000, # 0x18
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0xbaadf00d, # 0x1c
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]
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self.pattern_generator_test(pattern, expected, data_width=32, mem_depth=8)
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def test_pattern_generator_overwriting(self):
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pattern = [
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# address, data
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(0x00, 0xabadcafe),
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(0x07, 0xbaadf00d),
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(0x00, 0xcafefeed),
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(0x07, 0xdeadc0de),
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]
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expected = [
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# data, address
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0xcafefeed, # 0x00
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0x00000000, # 0x04
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0x00000000, # 0x08
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0x00000000, # 0x0c
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0x00000000, # 0x10
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0x00000000, # 0x14
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0x00000000, # 0x18
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0xdeadc0de, # 0x1c
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]
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self.pattern_generator_test(pattern, expected, data_width=32, mem_depth=8)
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def test_pattern_generator_sequential(self):
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length = 64
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prng = random.Random(42)
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address = [a for a in range(length)]
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data = prng.choices(range(2**32 - 1), k=length)
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pattern = list(zip(address, data))
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expected = [0x00000000] * 128
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for adr, data in pattern:
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expected[adr] = data
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self.pattern_generator_test(pattern, expected, data_width=32, mem_depth=128)
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def test_pattern_generator_random(self):
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length = 64
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prng = random.Random(42)
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address = [a for a in prng.sample(range(128), k=length)]
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data = prng.choices(range(2**32 - 1), k=length)
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pattern = list(zip(address, data))
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expected = [0x00000000] * 128
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for adr, data in pattern:
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expected[adr] = data
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self.pattern_generator_test(pattern, expected, data_width=32, mem_depth=128)
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def test_bist(self):
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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self.submodules.generator = _LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = _LiteDRAMBISTChecker(self.read_port)
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def main_generator(dut, mem):
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generator = GenCheckDriver(dut.generator)
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checker = GenCheckDriver(dut.checker)
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# write
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yield from generator.reset()
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yield from generator.configure(16, 64)
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yield from generator.run()
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# read (no errors)
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yield from checker.reset()
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yield from checker.configure(16, 64)
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yield from checker.run()
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assert checker.errors == 0
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# corrupt memory (using generator)
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yield from generator.reset()
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yield from generator.configure(16 + 60, 64)
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yield from generator.run()
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# read (4 errors)
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yield from checker.reset()
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yield from checker.configure(16, 64)
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yield from checker.run()
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assert checker.errors != 0
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# read (no errors)
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yield from checker.reset()
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yield from checker.configure(16 + 60, 64)
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yield from checker.run()
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assert checker.errors == 0
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# dut
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dut = DUT()
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mem = DRAMMemory(32, 128)
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# simulation
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generators = [
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main_generator(dut, mem),
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mem.write_handler(dut.write_port),
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mem.read_handler(dut.read_port)
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]
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run_simulation(dut, generators)
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