151 lines
5.0 KiB
Python
Executable File
151 lines
5.0 KiB
Python
Executable File
import unittest
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import random
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from migen import *
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from litedram.common import LiteDRAMNativePort
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from litedram.frontend.axi import *
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from litex.gen.sim import *
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class TestAXI(unittest.TestCase):
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def test_axi2native(self):
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def writes_generator(axi_port):
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yield axi_port.b.ready.eq(1) # always accepting write response
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for i in range(16):
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# command
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yield axi_port.aw.valid.eq(1)
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yield axi_port.aw.addr.eq(i)
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yield
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while (yield axi_port.aw.ready) == 0:
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yield
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yield axi_port.aw.valid.eq(0)
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yield
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# data
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yield axi_port.w.valid.eq(1)
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yield axi_port.w.data.eq(i)
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yield
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while (yield axi_port.w.ready) == 0:
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yield
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yield axi_port.w.valid.eq(0)
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yield
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def reads_generator(axi_port):
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yield axi_port.r.ready.eq(1) # always accepting read response
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for i in range(16):
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# command
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yield axi_port.ar.valid.eq(1)
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yield axi_port.ar.addr.eq(i)
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yield
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while (yield axi_port.ar.ready) == 0:
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yield
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yield axi_port.ar.valid.eq(0)
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yield
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# data
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while (yield axi_port.r.valid) == 0:
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yield
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yield
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@passive
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def dram_generator(dram_port):
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yield dram_port.cmd.ready.eq(1)
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yield dram_port.wdata.ready.eq(1)
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while True:
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yield dram_port.rdata.valid.eq(0)
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if (yield dram_port.cmd.valid):
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if (yield dram_port.cmd.we) == 0:
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yield dram_port.rdata.valid.eq(1)
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yield
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# dut
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axi_port = LiteDRAMAXIPort(32, 32, 32)
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dram_port = LiteDRAMNativePort("both", 32, 32)
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dut = LiteDRAMAXI2Native(axi_port, dram_port)
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# simulation
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generators = [
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writes_generator(axi_port),
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reads_generator(axi_port),
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dram_generator(dram_port)
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]
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run_simulation(dut, generators, vcd_name="axi2native.vcd")
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def test_burst2beat(self):
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class Beat:
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def __init__(self, addr):
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self.addr = addr
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class Burst:
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def __init__(self, type, addr, len, size):
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self.type = type
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self.addr = addr
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self.len = len
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self.size = size
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def to_beats(self):
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r = []
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for i in range(self.len + 1):
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if self.type == burst_types["incr"]:
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r += [Beat(self.addr + i*2**(self.size))]
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else:
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r += [Beat(self.addr)]
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return r
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def bursts_generator(ax, bursts, valid_rand=50):
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prng = random.Random(42)
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for burst in bursts:
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yield ax.valid.eq(1)
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yield ax.addr.eq(burst.addr)
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yield ax.burst.eq(burst.type)
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yield ax.len.eq(burst.len)
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yield ax.size.eq(burst.size)
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while (yield ax.ready) == 0:
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yield
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yield ax.valid.eq(0)
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while prng.randrange(100) < valid_rand:
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yield
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yield
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@passive
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def beats_checker(ax, beats, ready_rand=50):
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self.errors = 0
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yield ax.ready.eq(0)
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prng = random.Random(42)
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for beat in beats:
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while ((yield ax.valid) and (yield ax.ready)) == 0:
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if prng.randrange(100) > ready_rand:
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yield ax.ready.eq(1)
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else:
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yield ax.ready.eq(0)
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yield
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ax_addr = (yield ax.addr)
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if ax_addr != beat.addr:
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self.errors += 1
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yield
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# dut
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ax_burst = stream.Endpoint(ax_description(32, 32))
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ax_beat = stream.Endpoint(ax_description(32, 32))
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dut = LiteDRAMAXIBurst2Beat(ax_burst, ax_beat)
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# generate dut input (bursts)
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prng = random.Random(42)
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bursts = []
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for i in range(32):
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bursts.append(Burst(burst_types["fixed"], prng.randrange(2**32), prng.randrange(256), log2_int(32//8)))
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bursts.append(Burst(burst_types["incr"], prng.randrange(2**32), prng.randrange(256), log2_int(32//8)))
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# generate expexted dut output (beats for reference)
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beats = []
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for burst in bursts:
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beats += burst.to_beats()
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# simulation
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generators = [
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bursts_generator(ax_burst, bursts),
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beats_checker(ax_beat, beats)
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]
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run_simulation(dut, generators, vcd_name="burst2beat.vcd")
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self.assertEqual(self.errors, 0)
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