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litedram/litedram/frontend
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Florent Kermarrec f1dba787f6 frontend/dma/LiteDRAMDMAWriter/add_csr: add missing sink.valid
2020-02-19 18:34:55 +01:00
..
__init__.py init from LiteX/MiSoC 2016-04-29 07:44:30 +02:00
adaptation.py global: improve presentation/readability 2019-11-30 10:53:11 +01:00
axi.py global: improve presentation/readability 2019-11-30 10:53:11 +01:00
bist.py frontend/bist: regroup random_data/random_addr in the same CSRStorage to keep software retro-compatibility 2020-02-15 16:24:59 +01:00
dma.py frontend/dma/LiteDRAMDMAWriter/add_csr: add missing sink.valid 2020-02-19 18:34:55 +01:00
ecc.py global: improve presentation/readability 2019-11-30 10:53:11 +01:00
fifo.py frontend/fifo: get back to original simple design and add test 2020-01-07 15:40:09 +01:00
wishbone.py frontend/wishbone: round port_data_width to lowest power of 2 (required for ECC cases) 2020-02-10 09:56:36 +01:00