Florent Kermarrec 043666672d phy/gensdrphy: sample rddata on sys_clk (assume clk generated to sdram is shifted), add cmd_latency parameter and simplify control logic.		2020-03-24 19:50:35 +01:00
..
core	core/controller: cleanup ControllerSettings	2019-12-03 12:16:50 +01:00
frontend	frontend/dma/LiteDRAMDMAWriter/add_csr: add missing sink.valid	2020-02-19 18:34:55 +01:00
phy	phy/gensdrphy: sample rddata on sys_clk (assume clk generated to sdram is shifted), add cmd_latency parameter and simplify control logic.	2020-03-24 19:50:35 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common: PHYPadsCombiner: add "dqs" to the list	2020-03-11 15:01:25 +01:00
dfii.py	global: improve presentation/readability	2019-11-30 10:53:11 +01:00
gen.py	Allow specifying builder arguments for standalone generator	2020-03-17 20:02:18 +01:00
init.py	modules/init: add DDR4 fine refresh mode support: x1, x2 and x4 (x1=previous and default behavior)	2019-12-03 12:20:32 +01:00
modules.py	modules: add MT40A512M8 DDR4.	2020-03-10 13:56:13 +01:00