litedram/litedram/phy
2020-03-24 19:50:35 +01:00
..
__init__.py phy/usddrphy: add USPDDRPHY and rename sim_device parameter to device. 2020-03-10 16:07:53 +01:00
dfi.py phy/usddrphy: move DDR4DFIMux to dfi.py 2019-09-11 08:57:58 +02:00
ecp5ddrphy.py phys: integrate PHYPadsCombiner. 2020-03-06 18:56:28 +01:00
gensdrphy.py phy/gensdrphy: sample rddata on sys_clk (assume clk generated to sdram is shifted), add cmd_latency parameter and simplify control logic. 2020-03-24 19:50:35 +01:00
model.py Fix copyrights 2020-03-05 17:40:21 +01:00
s6ddrphy.py s6ddrphy/s7ddrphy: use IOBUFDS/IOBUF for DQS even if input is not currently used. 2020-03-19 18:15:08 +01:00
s7ddrphy.py phy/s7ddrphy: add ISERDESE2 MEMORY mode support that uses DQS to sample the DQ datas. 2020-03-20 18:54:23 +01:00
usddrphy.py phy/usddrphy: add assertions on iodelay_clk_freq. 2020-03-10 16:40:44 +01:00