Florent Kermarrec 2bdeda021b move standalone core generation to litedram package and make it usable externally ... When LiteDRAM is installed, standalone core can now be generated with "litedram_gen config.yml"		2019-08-28 07:19:30 +02:00
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__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	test: remove use of rand_wait, rename rand_level to random	2019-07-23 21:14:17 +02:00
test_adaptation.py	test/test_adaption: use same DUT for up/down converter tests	2019-07-13 10:52:41 +02:00
test_axi.py	test: remove use of rand_wait, rename rand_level to random	2019-07-23 21:14:17 +02:00
test_bist.py	test/test_bist: remove vcd generation (only useful for debug)	2019-07-23 21:46:03 +02:00
test_ecc.py	test: -x on tests	2019-07-23 12:16:44 +02:00
test_examples.py	move standalone core generation to litedram package and make it usable externally	2019-08-28 07:19:30 +02:00
test_refresh.py	core/refresher: add capability to accumulate N refreshs and execute the N refreshs together	2019-08-14 09:57:24 +02:00
test_timing.py	test: rename test_timing_controllers to test_timing	2019-07-23 16:05:31 +02:00